////////////////////////////////////////////////////////////////////////////// 
//
//  gen_sync.v
//
//  Generic clock domain crossing synchronizer.  Simply stages a signal
//  through three flops to protect against metastability.  Requires that
//  sampling clock is faster than source clock.
//
//  Original Author: 
//  Current Owner:   
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/gen_pipe_dly.v $
//    $DateTime: 2013/12/17 07:13:28 $
//    $Revision: #2 $
//
////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/10fs
module np_gen_pipe_dly #(parameter RST_VAL=0, parameter PIPE_DLY=1) (
output wire q,
input  wire rst,
input  wire clk,
input  wire d
);

// Create a version of the input which is synchronized with the local clock
//
// %%SYNTH:
//   set_false_path -from $nonscan_clks -to $inst/d_s1_reg/next_state
//   set_false_path -from $scan_clks -through $inst/d_s1_reg/next_state -to $nonscan_clks
//
generate
  if (PIPE_DLY == 8) begin: pipe_dly_8_gen
  reg  d_s1, d_s2, d_s3, d_s4, d_s5, d_s6, d_s7, d_s8;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
        d_s4 <= RST_VAL;
        d_s5 <= RST_VAL;
        d_s6 <= RST_VAL;
        d_s7 <= RST_VAL;
        d_s8 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
        d_s4 <= d_s3;
        d_s5 <= d_s4;
        d_s6 <= d_s5;
        d_s7 <= d_s6;
        d_s8 <= d_s7;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s8;
  end
  else if (PIPE_DLY == 7) begin: pipe_dly_7_gen
  reg  d_s1, d_s2, d_s3, d_s4, d_s5, d_s6, d_s7;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
        d_s4 <= RST_VAL;
        d_s5 <= RST_VAL;
        d_s6 <= RST_VAL;
        d_s7 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
        d_s4 <= d_s3;
        d_s5 <= d_s4;
        d_s6 <= d_s5;
        d_s7 <= d_s6;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s7;
  end
  else if (PIPE_DLY == 6) begin: pipe_dly_6_gen
  reg  d_s1, d_s2, d_s3, d_s4, d_s5, d_s6;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
        d_s4 <= RST_VAL;
        d_s5 <= RST_VAL;
        d_s6 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
        d_s4 <= d_s3;
        d_s5 <= d_s4;
        d_s6 <= d_s5;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s6;
  end
  else if (PIPE_DLY == 5) begin: pipe_dly_5_gen
  reg  d_s1, d_s2, d_s3, d_s4, d_s5;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
        d_s4 <= RST_VAL;
        d_s5 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
        d_s4 <= d_s3;
        d_s5 <= d_s4;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s5;
  end
  else if (PIPE_DLY == 4) begin: pipe_dly_4_gen
  reg  d_s1, d_s2, d_s3, d_s4;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
        d_s4 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
        d_s4 <= d_s3;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s4;
  end
  else if (PIPE_DLY == 3) begin: pipe_dly_3_gen
  reg  d_s1, d_s2, d_s3;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
        d_s3 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
        d_s3 <= d_s2;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s3;
  end
  else if (PIPE_DLY == 2) begin: pipe_dly_2_gen
  reg  d_s1, d_s2;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
        d_s2 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
        d_s2 <= d_s1;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s2;
  end
  else begin: pipe_dly_1_gen
  reg  d_s1;
    always @(posedge clk or posedge rst) begin
      if (rst) begin
        d_s1 <= RST_VAL;
      end 
      else begin
        d_s1 <= d;
      end
    end // always @ (posedge clk or posedge rst)
    assign q = d_s1;
  end
endgenerate

// ASSERT: add assertion that d never is too short for clk to capture reliably
   
endmodule
